The present invention relates generally to optical lithographic techniques commonly used in the formation of integrated circuits and structures on a semiconductor substrate. In particular, the present invention relates to methods of correcting a mask for use in photolithography, systems to perform the correction and apparatus produced from such a corrected mask.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright (copyright) 1999, Micron Technology, Inc., All Rights Reserved.
Semiconductor device features are primarily fabricated using photolithography. The art of photolithography embodies techniques for creating two-dimensional patterns on a work surface, or target, by the controlled application of energy (such as electromagnetic, ion beam or other radiation) to a reactive material, or resist, deposited on the target. In a photolithographic process, the energy application is controlled through the use of a patterned photomask. The pattern is transferred to a resist coating on the target, forming a resist pattern. The target is then etched according to the resist pattern and, following the etch, subjected to further processing steps. In semiconductor fabrication, the target may be a semiconductor wafer and the resulting features form a portion of a final integrated circuit.
Typically, photolithography is achieved by projecting or transmitting energy through a pattern made of opaque areas and clear areas on a mask. In the case of optical photolithography, the opaque areas of the pattern block light, thereby casting shadows and creating dark areas, while the clear areas allow light to pass, thereby creating light areas. Energy is projected through the clear areas onto and through a lens and subsequently onto the target, such as a semiconductor wafer. The term opaque refers to any area that blocks a sufficient level of the projected energy such that any energy passing through the opaque area will produce only negligible reaction with the resist coating. The term clear refers to any area that permits a sufficient level of energy to project onto the target to react with the resist coating to produce a resist pattern. The resist pattern is used to protect portions of an underlying substrate during subsequent removal techniques, such as etching, to form a patterned layer on the substrate substantially duplicating the resist pattern.
In the process of forming a patterned layer through the use of a projection exposure, it is customary that a member used for reduced-size projection is termed a reticle, and a member for life-size projection is termed a mask; or a member corresponding to an original sheet is termed a reticle, and a member obtained by duplicating such a reticle is termed a mask. In the present invention, any of the masks and reticles classified by such various definitions are referred to as a mask for convenience. Furthermore, the term mask may also refer to a database representation used to produce a physical mask.
The process of producing a mask for an integrated circuit involves generating a composite drawing of the integrated circuit derived from a circuit layout, which is generated from the functional and schematic diagrams. The composite drawing represents the various layers of the integrated circuit, and each layer of the composite drawing will be used to generate a single mask. To transform a layer of the composite drawing into a mask, it is digitized. The resulting database representation defines the opaque and clear areas of the mask. The physical mask is typically produced by selectively establishing areas of opaque material, often a layer of chrome, on a clear support, often a glass or quartz plate. As will be apparent to the reader, areas of the clear support not covered by the opaque material are necessarily clear.
Because of increased semiconductor device complexity that results in increased pattern complexity, and increased pattern packing density on the mask, it is becoming increasingly difficult to produce a precise pattern image despite advances in photolithographic techniques. One problem leading to increased difficulty in transferring a pattern from a mask to the target is overlay error. Overlay error occurs where two discrete patterned layers are formed using masks on two separate lithography systems. Each lithography system will have a distortion fingerprint, i.e., imperfections in the lens and stepper mechanisms resulting in a translation or offset between the intended placement of an image feature and the actual placement of its projected image. Where one lithography system is used to produce a pattern on a first layer and a second lithography system is used to produce a pattern on a second layer, the differences in their distortion fingerprints result in a relative offset between corresponding features of the two patterns A common situation includes two lithography systems, with one having a larger field of exposure than the other. The exposure from the lithography system having the smaller field of exposure is reproduced usually two or more times in the field of exposure of the other lithography system. Another situation is simply where one exposure from one lithography system overlays an exposure from another lithography system.
Translation, rotation and magnification have been used to minimize overlay error. Despite such corrections for overlay error, features will still experience offset. This residual offset may be unacceptable as feature dimensions continue to decrease.
As can be seen, the accuracy of the mask pattern and the resulting resist pattern play important roles in the quality of the circuit. As feature size decreases, the impact of offset increases proportionately. As manufacturing requirements call for exposure of patterns with smaller and smaller dimensions, it is becoming necessary to employ techniques that permit enhancement of the current performance of the process of photolithography.
Methods are disclosed wherein a photolithographic mask is corrected based on overlay error values for various zones across a field. A variety of semiconductor circuits, dies, modules and electronic systems may be produced from masks produced in accordance with the invention. Such apparatus exhibit improved uniformity of features at the circuit level of the apparatus due to a decrease in overlay error not possible through conventional overlay error correction.
In one embodiment, the invention provides a method of correcting a photolithographic mask involving determining overlay error variation across a field of the mask and defining at least two zones within the field of the mask, wherein each zone is a continuous portion of the field containing substantially similar overlay error values, and wherein each zone has a nominal overlay error value. The method further includes defining a correction for each of the at least two zones, wherein the correction for each zone is approximately the nominal overlay error value for that zone, mapping a feature of the mask to one of the at least two zones, and modifying coordinates of the feature in response to the correction for the zone to which the feature is mapped. In a further embodiment, the invention provides photolithographic masks wherein features on the mask exhibit overlay error corrections based on zones within a field of the mask.
In another embodiment, the invention provides a method of producing a photolithographic mask involving generating a database representation of a physical mask, correcting the database representation for overlay error, and selectively establishing opaque areas on a clear support in response to the corrected database representation. Correcting for overlay error includes determining overlay error variation across a field of the mask and defining at least two zones within the field of the mask, wherein each zone is a continuous portion of the field containing substantially similar overlay error values, and wherein each zone has a nominal overlay error value. Correcting for overlay error further includes defining a correction for each of the at least two zones, wherein the correction for each zone is approximately the nominal overlay error value for that zone, mapping each of a plurality of features to one of the at least two zones, and modifying coordinates of each of the plurality of features in response to the correction for the zone in which each feature is mapped. Selectively establishing opaque areas includes selectively depositing opaque material on a portion of a support, as well as depositing a layer of opaque material on a support and selectively removing portions of that layer.
In another embodiment, the invention provides a computer program for correcting pattern features for overlay error based on the overlay error values across the field of exposure. In a further embodiment, the invention provides a machine readable medium having instructions stored thereon for correction of pattern features for overlay error based on the overlay error values across the field of exposure. In a still further embodiment, the invention provides a system for correcting pattern features for overlay error based on the overlay error values across the field of exposure, wherein the system has such a machine readable medium.
The invention further includes methods of varying scope, apparatus produced by the methods, and systems useful in performing the methods.
FIG. 1 is a schematic of a photolithography projection system.
FIG. 2 is a high-level flowchart depicting one embodiment of a method of the invention.
FIG. 3A is an elevation view of an exemplary test pattern.
FIG. 3B is a schematic of the components of overlay error.
FIG. 4 is a conceptualization of zones defined in a field of exposure for use in the invention.
FIG. 5 is a high-level flowchart depicting one subprocess of the method depicted in FIG. 2.
FIG. 6 is a high-level flowchart depicting an alternate subprocess of the method depicted in FIG. 2.
FIG. 7 is an elevation view of a substrate containing semiconductor dies.
FIG. 8 is a block diagram of an exemplary circuit module.
FIG. 9 is a block diagram of an exemplary memory module.
FIG. 10 is a block diagram of an exemplary electronic system.
FIG. 11 is a block diagram of an exemplary memory system.
FIG. 12 is a block diagram of an exemplary computer system.